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integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 1 rev. b 06/28/02 is61lv25616l issi ? copyright ? 2002 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. features ? high-speed access time: ? 10, 12, and 15 ns low active power ? less than 90ma (typ.) active current low standby power: ? less than 1 m a (typ.) cmos standby ttl compatible interface levels single 3.3v power supply fully static operation: no clock or refresh required three state outputs data control for upper and lower bytes industrial temperature available 256k x 16 high speed asynchronous cmos static ram with 3.3v supply description the issi is61lv25616l is a high-speed, 4,194,304-bit static ram organized as 262,144 words by 16 bits. it is fabricated using issi 's high-performance cmos technol- ogy. this highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. when ce is high (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with cmos input levels. easy memory expansion is provided by using chip enable and output enable inputs, ce and oe . the active low write enable ( we ) controls both writing and reading of the memory.a data byte allows upper byte ( ub ) and lower byte ( lb ) access. the is61lv25616l is packaged in the jedec standard 44-pin 400-mil soj, 44-pin tsop type ii, 44-pin lqfp and 48-pin mini bga (8mm x 10mm). functional block diagram a0-a17 ce oe we 256k x 16 memory array decoder column i/o control circuit gnd vcc i/o data circuit i/o0-i/o7 lower byte i/o8-i/o15 upper byte ub lb june 2002
2 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. b 06/28/02 is61lv25616l issi ? pin descriptions a0-a17 address inputs i/o0-i/o15 data inputs/outputs ce chip enable input oe output enable input we write enable input lb lower-byte control (i/o0-i/o7) ub upper-byte control (i/o8-i/o15) nc no connection vcc power gnd ground 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 a0 a1 a2 a3 a4 ce i/o0 i/o1 i/o2 i/o3 vcc gnd i/o4 i/o5 i/o6 i/o7 we a5 a6 a7 a8 a9 a17 a16 a15 oe ub lb i/o15 i/o14 i/o13 i/o12 gnd vcc i/o11 i/o10 i/o9 i/o8 nc a14 a13 a12 a11 a10 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 ce i/o0 i/o1 i/o2 i/o3 vcc gnd i/o4 i/o5 i/o6 i/o7 i/o15 i/o14 i/o13 i/o12 gnd vcc i/o11 i/o10 i/o9 i/o8 nc top view we a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a17 a16 a15 a14 a13 a12 a11 a10 oe ub lb pin configurations 44-pin tsop (type ii) and soj 44-pin lqfp 1 2 3 4 5 6 a b c d e f g h lb oe a0 a1 a2 n/c i/o 8 ub a3 a4 ce i/o 0 i/o 9 i/o 10 a5 a6 i/o 1 i/o 2 gnd i/o 11 a17 a7 i/o 3 vcc vcc i/o 12 nc a16 i/o 4 gnd i/o 14 i/o 13 a14 a15 i/o 5 i/o 6 i/o 15 nc a12 a13 we i/o 7 nc a8 a9 a10 a11 nc 48-pin mini bga
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 3 rev. b 06/28/02 1 2 3 4 5 6 7 8 9 10 11 12 is61lv25616l issi ? truth table i/o pin mode i/o0-i/o7 i/o8-i/o15 vcc current not selected x h x x x high-z high-z i sb 1 , i sb 2 output disabled h l h x x high-z high-z i cc x l x h h high-z high-z read h l l l h d out high-z i cc h l l h l high-z d out hllll d out d out write l l x l h d in high-z i cc l l x h l high-z d in llxll d in d in absolute maximum ratings (1) symbol parameter value unit v term terminal voltage with respect to gnd ?0.5 to vcc+0.5 v t bias temperature under bias ?45 to +90 c v cc vcc related to gnd ?0.3 to +4.0 v t stg storage temperature ?65 to +150 c p t power dissipation 1.0 w note: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. operating range 10 ns 12 ns, 15 ns range ambient temperature v cc v cc commercial 0c to +70c 3.3v +10%, -5% 3.3v 10% industrial ?40c to +85c 3.3v +10%, -5% 3.3v 10%
4 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. b 06/28/02 is61lv25616l issi ? capacitance (1) symbol parameter conditions max. unit c in input capacitance v in = 0v 6 pf c out input/output capacitance v out = 0v 8 pf note: 1. tested initially and after any design or process changes that may affect these parameters. power supply characteristics (1) (over operating range) -10 -12 -15 symbol parameter test conditions min. max. min. max. min. max. unit i cc vcc dynamic operating v cc = max., com. ? 125 ? 115 ? 105 ma supply current i out = 0 ma, f = f max ind. ? 135 ? 125 ? 115 i sb ttl standby current v cc = max., com. ? 65 ? 55 ? 45 ma (ttl inputs) v in = v ih or v il ind. ? 70 ? 60 ? 50 ce v ih , f = f max . i sb 1 ttl standby current v cc = max., com. ? 15 ? 15 ? 15 ma (ttl inputs) v in = v ih or v il ind. ? 20 ? 20 ? 20 ce v ih , f = 0 i sb 2 cmos standby v cc = max., com. ? 5 ? 5 ? 5 ma current (cmos inputs) ce v cc ? 0.2v, ind. ? 10 ? 10 ? 10 v in v cc ? 0.2v, or v in 0.2v, f = 0 note: 1. at f = f max , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. shaded area product in development dc electrical characteristics (over operating range) symbol parameter test conditions min. max. unit v oh output high voltage v cc = min., i oh = ?4.0 ma 2.4 ? v v ol output low voltage v cc = min., i ol = 8.0 ma ? 0.4 v v ih input high voltage 2.0 v cc + 0.3 v v il input low voltage (1) ?0.3 0.8 v i li input leakage gnd v in v cc com. ?1 1 a ind. ?5 5 i lo output leakage gnd v out v cc , 4 com. ?1 1 a outputs disabled ind. ?5 5 notes: 1. v il (min.) = ?2.0v for pulse width less than 10 ns.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 5 rev. b 06/28/02 1 2 3 4 5 6 7 8 9 10 11 12 is61lv25616l issi ? read cycle switching characteristics (1) (over operating range) -10 -12 -15 symbol parameter min. max. min. max. min. max. unit t rc read cycle time 10 ? 12 ? 15 ? ns t aa address access time ? 10 ? 12 ? 15 ns t oha output hold time 3 ? 3 ? 3 ? ns t ace ce access time ? 10 ? 12 ? 15 ns t doe oe access time ? 4 ? 5 ? 7 ns t hzoe (2) oe to high-z output ? 4 ? 5 0 6 ns t lzoe (2) oe to low-z output 0 ? 0 ? 0 ? ns t hzce (2 ce to high-z output 0 4 0 6 0 8 ns t lzce (2) ce to low-z output 3 ? 3 ? 3 ? ns t ba lb , ub access time ? 4 ? 5 ? 7 ns t hzb (2) lb , ub to high-z output 0 3 0 4 0 5 ns t lzb (2) lb , ub to low-z output 0 ? 0 ? 0 ? ns t pu power up time 0 ? 0 ? 0 ? ns t pd power down time ? 10 ? 12 ? 15 ns notes: 1. test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0v to 3.0v and output loading specified in figure 1. 2. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage. shaded area product in development ac test conditions parameter unit input pulse level 0v to 3.0v input rise and fall times 3 ns input and output timing 1.5v and reference level output load see figures 1 and 2 ac test loads figure 1 figure 2 319 ? 5 pf including jig and scope 353 ? output 3.3v 319 ? 30 pf including jig and scope 353 ? output 3.3v
6 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. b 06/28/02 is61lv25616l issi ? data valid read1.eps previous data valid t aa t oha t oha t rc d out address t rc t oha t aa t doe t lzoe t ace t lzce t hzoe high-z data valid ub_cedr2.eps t hzb address oe ce lb, ub d out t hzce t ba t lzb t rc t pd i sb i cc 50% v cc supply current 50% t pu read cycle no. 2 (1,3) ac waveforms read cycle no. 1 (1,2) (address controlled) ( ce = oe = v il , ub or lb = v il ) notes: 1. we is high for a read cycle. 2. the device is continuously selected. oe , ce , ub , or lb = v il . 3. address is valid prior to or coincident with ce low transition.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 7 rev. b 06/28/02 1 2 3 4 5 6 7 8 9 10 11 12 is61lv25616l issi ? write cycle switching characteristics (1,3) (over operating range) -10 -12 -15 symbol parameter min. max. min. max. min. max. unit t wc write cycle time 10 ? 12 ? 15 ? ns t sce ce to write end 8 ? 8 ? 10 ? ns t aw address setup time 8 ? 8 ? 10 ? ns to write end t ha address hold from write end 0 ? 0 ? 0 ? ns t sa address setup time 0 ? 0 ? 0 ? ns t pwb lb , ub valid to end of write 8 ? 8 ? 10 ? ns t pwe 1 we pulse width 8 ? 8 ? 10 ? ns t pwe 2 we pulse width ( oe = low) 10 ? 12 ? 12 ? ns t sd data setup to write end 6 ? 6 ? 7 ? ns t hd data hold from write end 0 ? 0 ? 0 ? ns t hzwe (2) we low to high-z output ? 5 ? 6 ? 7 ns t lzwe (2) we high to low-z output 2 ? 2 ? 2 ? ns notes: 1. test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0v to 3.0v and output loading specified in figure 1. 2. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage. not 100% tested. 3. the internal write time is defined by the overlap of ce low and ub or lb , and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to t he rising or falling edge of the signal that terminates the write. shaded area product in development
8 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. b 06/28/02 is61lv25616l issi ? notes: 1. write is an internally generated signal asserted during an overlap of the low states on the ce and we inputs and at least one of the lb and ub inputs being in the low state. 2. write = ( ce ) [ ( lb ) = ( ub ) ] ( we ). ac waveforms write cycle no. 1 ( ce controlled, oe is high or low) (1 ) data undefined t wc valid address t sce t pwe1 t pwe2 t aw t ha high-z t pbw t hd t sa t hzwe address ce ub, lb we d out d in data in valid t lzwe t sd ub_cewr1.eps
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 9 rev. b 06/28/02 1 2 3 4 5 6 7 8 9 10 11 12 is61lv25616l issi ? ac waveforms write cycle no. 2 ( we controlled. oe is high during write cycle) (1,2) data undefined low t wc valid address t pwe1 t aw t ha high-z t pbw t hd t sa t hzwe address ce ub, lb we d out d in oe data in valid t lzwe t sd ub_cewr2.eps write cycle no. 3 ( we controlled. oe is low during write cycle) (1) data undefined t wc valid address low low t pwe2 t aw t ha high-z t pbw t hd t sa t hzwe address ce ub, lb we d out d in oe data in valid t lzwe t sd ub_cewr3.eps
10 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. b 06/28/02 is61lv25616l issi ? ac waveforms write cycle no. 4 ( lb , ub controlled, back-to-back write) (1,3) data undefined t wc address 1 address 2 t wc high-z t pbw word 1 low word 2 ub_cewr4.eps t hd t sa t hzwe address ce ub, lb we d out d in oe data in valid t lzwe t sd t pbw data in valid t sd t hd t sa t ha t ha notes: 1. the internal write time is defined by the overlap of ce = low, ub and/or lb = low, and we = low. all signals must be in valid states to initiate a write, but any can be deasserted to terminate the write. the t sa , t ha , t sd , and t hd timing is referenced to the rising or falling edge of the signal that terminates the write. 2. tested with oe high for a minimum of 4 ns before we = low to place the i/o in a high-z state. 3. we may be held low across many address cycles and the lb , ub pins can be used to control the write function.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 11 rev. b 06/28/02 1 2 3 4 5 6 7 8 9 10 11 12 is61lv25616l issi ? ordering information commercial range: 0c to +70c speed order part no. package (ns) 10 is61lv25616l-10t tsop (type ii) is61lv25616l-10k 400-mil soj is61lv25616l-10lq lqfp is61lv25616l-10b mini bga (8mm x 10mm) 12 is61lv25616l-12t tsop (type ii) is61lv25616l-12k 400-mil soj is61lv25616l-12lq lqfp is61lv25616l-12b mini bga (8mm x 10mm) 15 is61lv25616l-15t tsop (type ii) IS61LV25616L-15K 400-mil soj industrial range: ?40c to +85c speed order part no. package (ns) 10 is61lv25616l-10ti tsop (type ii) is61lv25616l-10ki 400-mil soj is61lv25616l-10lqi lqfp is61lv25616l-10bi mini bga (8mm x 10mm) 12 is61lv25616l-12ti tsop (type ii) is61lv25616l-12ki 400-mil soj is61lv25616l-12lqi lqfp is61lv25616l-12bi mini bga (8mm x 10mm) 15 is61lv25616l-15ti tsop (type ii) IS61LV25616L-15Ki 400-mil soj

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